During the early 1990s, Peripheral Component Interconnect (PCI) standards were introduced. PCI provided direct access to the system memory for connected devices, by using bridges to connect to front-side buses and to CPU. PCIs can connect multiple components. A PCI bridge chip may regulate the speed of a PCI bus independent from the CPU's speed to enable a higher degree of reliability, and to ensure that PCI hardware manufacturers have consistent design constraints. PCI supports Plug-and-Play, which enables a device or card to be inserted into a computer and automatically recognized and configured to work with that system.
Today's software applications are more demanding in the performance of platform hardware, particularly the I/O subsystems. Streaming data from various video and audio sources are now commonplace on the desktop and mobile machines. Applications such as video-on-demand and audio redistribution are putting increasingly stricter real-time constraints on servers. As a result, existing PCI architecture can no longer cope with these demands, and a new standard called PCI Express has been proposed.
Because the PCI Express standard is derived from and is backward compatible with PCI, the logical buses, devices, and functions within a PCI Express switch need to be compatible with PCI hierarchical guidelines. Conceptually, a PCI Express switch is a mix of PCI-to-PCI (P2P) bridges and internal endpoints, wherein each P2P bridge or internal end-point represents a single logical PCI function, and each PCI Express port represents a logical P2P bridge.
Typically, since a PCI Express switch (sometimes referred to as PCIe switch) will include multiple PCI bridges, the switching logic of the PCI Express switch needs to know all the information regarding the ports in the PCI Express switch. This brings several possible problems. First, since data packets may come into a PCI Express switch from different ports simultaneously, the processing of one packet may be blocked by the processing of another packet coming in from a different port. This adversely affects the performance of the PCI Express switch. Second, since the routers in the PCI Express switch need to have knowledge of all of the ports, when a port is added or removed (in a new product), or if the configuration/topology of the switch is changed over the previous switch products, the routers need to be re-designed every time a new PCI Express switch product is desired. The intellectual property (IP) of the functional blocks, such as the routers in the PCI Express switches, thus have low reusability. Accordingly, new PCI Express switches having improved routing performance and increased IP reusability are needed.